In recent years it has become possible to implement many complex logic functions on a single semiconductor die utilizing the MOS technology, wherein thousands of MOSFETS (metal oxide semiconductor field effect transistor) or IGFETS (insulated gate field effect transistor), as they are also commonly called are utilized to implement such products as 4096 bit decoded random access memories, 8192 bit readonly only memories, and complete microprocessors. Input buffer circuits are required on all of these circuits in order to permit the MOS LSI chips to receive digital signals from the environment in which it will operate. Most of the input buffer circuits have been inverters or latchers of various types. In designing MOS input buffer circuits, the main problems to be overcome by the circuit designer have been to provide input buffer circuits which produce adequate logical "1" and logical "0" output levels (to be utilized by other circuitry within the MOS LSI circuit) in response to worst case input "1" and "0" logic levels over the ranges of permissible variations in power supply voltage levels, MOSFET threshold voltages and other MOS processing parameters. Although many MOS input buffer circuits have been designed, no one input buffer circuit has proven completely satisfactory for a wide range of practical applications.